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Contents > Logic Gates

Intermediate Gates

The inverter described previously consists of an O wedged between an L and a J. However, it is possible to implement an inverter with a single O-tetromino:

o -1 2 0

in i 0 0
out o 0 1

As shown in the animated constructions below, the input and output nodes overlap. When the input is 1, the overlap establishes an output of 0 before the O-tetromino drops. Though, when the input is 0, the output node is initially unassigned.

Intermediate NOT

_notLeft's compact size translates to smaller circuits, which should be motivation to use it frequently. But in practice, it is used sparingly because, when the input is 1, it fails to support the O-tetromino. If that O-tetromino leaks out of a circuit, it will plummet until it meets the surface of the pile, where it can interfere with other circuits. The resultant unpredictable behavior renders such circuits incompatible with an important optimization, described in a later section, which depends on consistent circuit operation.

To use _notLeft safely, the O-tetromino must be caught. This is practical only in the interior of circuits, where the surrounding components act as barriers. There, _notLeft and other leaky gates are relegated to processing intermediate values, hence the designation, “intermediate gates”. Their names start with an underscore to make them instantly distinguishable from ordinary gates.

Smaller circuits suggest faster processing. But the aforementioned optimization makes circuits built purely out of ordinary gates compute just as quickly despite their larger size. There is no justification for intermediate gates except that their compact nature effectuates aesthetically pleasing designs. That is the impetus behind the following variation of the intermediate inverter.

o -1 2 1

in i 0 0
out o 0 1

_notLeft2 nudges the O-tetromino right twice:

Intermediate NOT 2

The construction assumes the fall speed is slow enough to slide the O-tetromino across the surface of the input node when the input value is 0.

_notLeft2 is attached to the output of an ordinary OR gate to create an intermediate NOR gate:

or 0 0
_notLeft2 -1 2

in a -1 0
in b 0 0
out o 0 3

Its response to all possible inputs appears below.

Intermediate NOR

On line 2 of the code, if _notLeft2 is replaced with _notLeft, the intermediate NOR gate works just as well. However, when both inputs are 0, the vertical column of O-tetrominoes becomes lopsided, an aesthetically displeasing configuration.

_norLeft is found in the interior of the ordinary XOR gate to reduce its size and to guarantee the O-tetromino is always caught.

The “Left” in the names of these intermediate gates refers the side of the inputs nudged by the O-tetromino. Horizontally-reflected versions exist called _notRight, _notRight2, and _norRight.

The intermediate NAND gate, _nand, uses intermediate inverters to feed input complements into an ordinary OR gate:

_notLeft -1 0
_notRight 0 0
or 0 1

in a -1 0
in b 0 0
out o -1..0 3

Intermediate NAND leaks up to two O-tetrominoes:

Intermediate NAND

The intermediate AND gate, _andLeft, consists of an intermediate NAND in series with an intermediate inverter:

_nand 0 0
_notLeft2 -1 3

in a -1 0
in b 0 0
out o -1..0 4

Here is its responses to all inputs:

Intermediate AND

Its horizontally-reflected version goes by the name _andRight.

While a single intermediate NOR appears in the ordinary XOR, the intermediate XOR, _xor, employs three of them:

ih -2
ih 2
iv -4
iv 3
_norLeft 0 1
lu -2
ju 1
_norLeft -3 5
_norRight 3 5
ih -2
ih 2
or 0 9

in a -4..-1 0
in b 0..3 0
out o -1..0 11

Like the intermediate NAND and AND gates, intermediate XOR emits up to two O-tetrominoes:

Intermediate XOR

Other intermediate gates are possible. But aside from the intermediate NOR gate and the intermediate inverter it is based on, the rest are not used. Their petiteness and visual appeal are not compelling enough to use them over ordinary gates, which operate safely in all circumstances.

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